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Spectrum Digital, Inc
2.4.1 Audio PLL/VCXO Circuit/PLL1705 Clock Generator
The DM6437 EVM implements a multiple PLL clock generator for creating the Audio
clocks for the board.
In streaming video applications the audio and video sequences can lose
synchronization. The DM6437 uses a VCXO interpolation circuit to incrementally speed
up or slow down the STCLK input to allow for this synchronization to remain locked.
The PWM1 and timer inputs on DM6437 are used to control this feature. The PWM0
pin drives a PICX100-27W Voltage Controlled Oscillator which is and fed back into the
timer input pin.
The STCLK is also a source clock for the PLL1705 programmable PLL device. This
device creates the clocks for the AIC33 Codec, daughter card VIDCLK an AUDIOCLK.
The PLL1705 is programmable via an I 2 C and Expander U13. Software sequencing on
the I/O expander is required to interface correctly to the PLL1705’s programmable
inputs.
The diagram below is a simplified diagram of this clocking scheme.
To I/O Expander
P
P P
L
L
M
S
L L
L L
M M
C D
SCK03
SCK02
SCK01
SCK00
AUDIO_CLK
PLL1705
MCK02
MCK01
VID_CLK
DM6437
XT1
TIMER PWM1
IN
VCXO
Circuit Using
STCLK
PICX100-27
Figure 2-3, Audio PLL/VCXO Circuit/PLL1705 Clock Generator
2-5
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